For decades, Moore’s Law embodied an implicit contract with customers: more performance at lower cost per unit. That promise was driven forward by evolutions in transistor geometry. Now, new innovations no longer result in lower costs, and Moore’s Law itself must be redefined.
Capital intensity across the semiconductor value chain has surged to historic highs. Advanced process nodes demand multi-billion-dollar fabrication investments, while the tooling required to manufacture at the angstrom scale, notably extreme ultraviolet (EUV) lithography, has redefined fixed-cost structures. Concurrent localization mandates, driven by geopolitical imperatives, add structural overhead onto an already cost-heavy industry. Supply shocks compound these pressures. Most critically, transistor scaling no longer guarantees the proportional cost-per-unit declines that customers and OEMs expect.
While compute continues to improve as Moore predicted, it is no longer driven by the same evolutions in transistor geometry. In this context, persisting with expected automatic price erosion is strategically unsustainable. The industry must reset pricing norms around the delivered system value of semiconductor innovation, not around historical cost curves. This transition requires transparent customer communication, rigorous segmentation, and deliberate portfolio governance.
The era of reflexive price decline is ending. Without recalibration, leaders risk under-monetizing the innovations underpinning their competitive advantage.
A departure from the original cost assumptions of Moore’s Law
Intel founder Gordon Moore observed that the number of transistors on a chip doubled roughly every two years. Since then, the semiconductor industry’s pricing logic has been inseparable from Moore’s Law. This prediction did more than describe a technical trajectory. It embedded a commercial expectation: each generation of silicon would deliver more capability at a lower cost per transistor.
This, however, is no longer the case. Multiple converging forces have altered the cost dynamics of semiconductor manufacturing, breaking the link between node advancement and automatic cost decline.
Capital intensity at unprecedented scale
The investment required to build and equip a leading-edge fabrication facility has escalated dramatically. A single advanced-node fab now costs between $15–$20 billion. The ramp of pre-Extreme Ultraviolet (EUV) 14nm node capabilities in the 2010s cost less than half as much.
Industry-wide semiconductor capital expenditure was projected at approximately $160 billion for 2025. TSMC alone set its 2025 capital expenditure guidance to $40–42 billion, with roughly 70 percent allocated to advanced process technologies.
These higher costs above are due in part to the surging price of capital equipment. ASML’s current-generation EUV lithography systems start at approximately $220 million per unit, while the next-generation High-NA (Numerical Aperture) EUV machines cost around $380 million each. Future Hyper-NA systems, expected in the early 2030s, could exceed $700 million per unit. This represents a step-change in the fixed-cost base required to compete at the frontier.
The cost burdens can be seen in the attrition of manufacturers. A dozen competed at the leading edge in 2000, falling to six in 2010, and just three in 2026.
The stress of yield on cost-per-transistor trends
The most consequential shift is the reversal of a trend: at the 2nm node, shrinking transistors no longer translate into cheaper transistors. TSMC’s 2nm wafer pricing is projected at approximately $30,000 per wafer, a 50 percent increase over the 3nm node’s roughly $20,000 per wafer.
This is not a temporary anomaly. The transition from FinFET to gate-all-around (GAA) transistor architecture was not simply a further reduction in gate size, but a redefinition of a ‘gate.’
Some of the complexity-driven yield loss is solvable through more precise etching and nanowire construction. Some complexity boils down to electron behavior around gate oxides, which are only a few atoms thick. At such scales, the boundaries of physics become an operational and commercial hurdle. Performance is still improving along the expected trajectory of Moore’s Law, but with a new cost profile.
Geopolitical localization and structural overhead
Governments worldwide are investing heavily to localize semiconductor manufacturing capacity. The U.S. CHIPS Act, the European Chips Act, and comparable programs in Asia are reshaping the geographic footprint of fabrication. Chinese manufacturers have supply chain mandates requiring a certain percentage of sourcing domestically. TSMC alone has committed over $165 billion to U.S.-based fab investments.
While these initiatives address legitimate supply-chain resilience objectives, they also introduce structural cost premiums. Building and operating fabs outside established semiconductor clusters in East Asia is inherently more expensive due to differences in labor costs, supply chain proximity, and operational ecosystem maturity.
Whether this represents a permanent reconfiguration of the industry’s cost base remains to be seen. Simon-Kucher’s position is that commercial realities will remain the key driver of capital allocation to supply chains in the mid-to-long term. However, in the short-term, the experiment in nearshoring AI deployment will continue to be the primary force behind new ramps outside of East Asia.
The pricing imperative: Why the industry must recalibrate
Shifts in the underlying cost assumptions of Moore’s Law create an urgent commercial challenge. If semiconductor companies continue operating under the legacy pricing paradigm, they risk leaving significant value on the table. By accepting annual cost-down expectations from customers, offering aggressive forward pricing to win designs, and treating silicon as a commodity input, they will systematically under-monetize the innovation embedded in their products. They may also fail to cover costs.
The consequences are compounding. Underpriced innovation causes insufficient reinvestment in R&D and capacity, slowing technological progress and harming customers who depend on continued semiconductor innovation to power their product roadmaps. This leads to further attrition at the leading edge.
Meanwhile, the original ‘compute’ assumptions of Moore’s Law continue apace. Rather than transistor geometry, however, innovation is flowing upstream to chiplets, heterogeneous integration, and software optimization. This increases modularity and makes suppliers more interchangeable without a clear leading-edge advantage. In the search for returns, predictable cost, and performance gains fade. Customers will rightly demand proof of system-level value, measured in total cost of ownership.
It is imperative that the industry reframes the conversation from cost-per-transistor to value-per-system-function. A 2nm AI accelerator chip does not merely offer more transistors; it delivers orders-of-magnitude improvements in inference throughput, energy efficiency, and total cost of ownership for the data center. An advanced automotive semiconductor does not just occupy less die area; it enables Level 4 full-self-driving autonomy, functional safety certification, and software-defined vehicle architectures that transform platform economics.
Pricing must reflect this delivered value, not the historical trajectory of manufacturing cost curves.
A pricing framework for the ‘Moore Compute’ Era
Resetting semiconductor pricing norms requires deliberate action across multiple dimensions.
Transparent communication
The economics behind semiconductor manufacturing have fundamentally changed, but customers may lack this context. Rather than defending price increases, companies can proactively educate the value chain about the structural cost drivers and the value delivered by continued innovation. Leading with transparency, explaining why cost-down trajectories are no longer sustainable, and what customers receive in return, helps build strong commercial relationships.
Distinct value pools
Manufacturers should consider disaggregating pricing line items. A lump sum price helps pass through price increases for value not tied directly to specific KPIs (e.g., heat performance), but it cuts two ways. Expectation of price decreases can be better mitigated by leveraging the distinct pools of value within a single wafer price. Manufacturers may consider transparent fees for base silicon, supply assurance, performance, packaging, and support. Disaggregation connects the commercial transaction to the underlying value, typically bundled into a single Average Selling Price, and strengthens its defense.
Build price around risk
One value pool deserving special attention is risk. Supply risk, R&D risk, qualification risk, and roadmap risk are more salient than ever. Risk-sharing mechanisms, such as supply assurance and corresponding long-term purchase agreements, can be as valuable of a commercial lever as compute. Taking full advantage requires a developed commercial muscle that moves beyond product-level value calculations. An industry upcycle is the right time to develop it.
Structured segmentation
Not all customers derive the same value from leading-edge innovation. AI hyperscalers purchasing inference accelerators at scale have different willingness-to-pay than automotive OEMs. Pricing strategies must reflect these differences through rigorous segmentation by application, performance tier, volume commitment, and strategic value of the design win. Where possible, consider the value of the end product. One-size-fits-all pricing in a structurally cost-inflated environment risks margin erosion.
Deliberate portfolio governance
Semiconductor companies must make explicit choices about which nodes, products, and customer segments warrant leading-edge investment and price accordingly. The rise of chiplet architectures and heterogeneous integration offer a strategic lever: performance-critical logic can be manufactured at 2nm, with ancillary functions placed on more cost-effective mature nodes. Portfolio governance means aligning the right technology to the right application at the right price point. This requires a level of proactivity that is sometimes absent in an industry chasing the latest ramp.
Tailor pricing models in the new era
The industry’s pricing model was built for a bygone era where each new generation of technology delivered more performance at lower cost.
Capital intensity is at all-time highs, manufacturing complexity is accelerating, and geopolitical localization is adding permanent structural cost. For the first time, the cost per transistor at the leading edge is rising, not falling.
These are not cyclical headwinds but structural shifts that demand a fundamental rethinking of how semiconductor innovation is monetized. Companies that cling to legacy cost-down models will struggle to fund the investments needed to stay competitive.
The question is no longer whether pricing norms will change, but whether your organization will lead or be disrupted by that change.
Contributing author: Emery Engling
With two decades of semiconductor experience, Simon-Kucher has supported industry leaders through transformative cycles, from the rise of the data economy to AI acceleration, and to the global compute surge. We are well-positioned to anticipate what comes next and excited to serve as a strategic partner in shaping it.
